Fabric-based Switching and Higher Bandwidth Unlocks New Topologies for Disaggregation at the Rack Level
Astera Labs, a pioneer in purpose-built connectivity solutions for intelligent systems, welcomes the release of The Compute Express Link™ (CXL™) 3.0 specification announced by the CXL Consortium at Flash Memory Summit (FMS). The CXL Consortium is an industry standards body dedicated to advancing CXL technology offering high-bandwidth, low-latency connectivity between host processors and devices such as accelerators, memory buffers, and smart I/O devices.
“As a leader in system-aware connectivity solutions for composable, disaggregated, and scalable data center infrastructure, we are excited to support this new version of the CXL standard with its expanded capabilities,” said Sanjay Charagulla, Vice President and General Manager, Astera Labs. “We are eager to continue our contributions to the specification and look forward to introducing new purpose-built connectivity solutions based on CXL 3.0.”
Cloud data centers require large-scale heterogenous composable architectures to optimize performance and cost. As a result, industry adoption of the CXL 2.0 standard has grown rapidly as it enabled heterogeneous architecture and addressed memory bottlenecks for Artificial Intelligence (AI), Machine Learning (ML), and general-purpose compute applications. The new CXL 3.0 specification builds on previous specifications, doubling the bandwidth, introducing fabric capabilities, improving memory pooling and sharing, enhancing coherency, and expanding the scale of heterogenous composable architectures.
Astera Labs continues to leverage the CXL specification and deliver innovative data center infrastructure solutions. Astera Labs’ Aries PCIe® 5.0/CXL Retimers were the industry’s first-to-market solution to address data connectivity bottlenecks and enable the adoption of CXL. Last year, Astera Labs announced its Leo CXL Memory Connectivity SoC Platform, the industry’s first CXL solution for memory expansion and pooling to address memory bottlenecks.
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