Infrastructure Management

Cadence Accelerates Cloud Hyperscale Infrastructure

Cadence Design Systems


  • DSP-based, flex-rate multi-rate SerDes IP is optimized for PPA for next-generation compute, switching, storage, AI/ML and 5G SoCs
  • New architecture offers 25% power improvement, 40% area reduction and better design margins for high-reliability systems

Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric systems on chip (SoCs). The Cadence® 112G-LR PAM4 SerDes IP on TSMC’s N5 process delivers the power, performance and area (PPA) efficiency required to build the high-bandwidth and high-reliability products for next-generation cloud data centers. The innovative architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture, satisfying the increasing needs for higher performance and power efficiency in today’s data centers.

Cadence has built a large customer base by enabling different variances of PAM4 SerDes supporting XSR, VSR, MR and LR interconnect standards. Through various 112G-LR SerDes design wins and deep collaborations with leading hyperscale and data center customers, Cadence has incorporated specific enhancements in the third-generation product and currently has N5 test chips in-house that are undergoing characterization. Cadence has been working closely with early adopter customers on deploying the new 112G-LR SerDes IP in their 5nm SoC development and is ready to engage broadly with customers to enable next-generation designs. For more information on the 112G-LR SerDes, please visit

With the improved architecture, Cadence now offers an enhanced DSP with multiple floating decision feedback equalization (DFE) taps to enable more robust performance. The 1-112G gapless data rate support provides excellent I/O flexibility for chip-to-chip connectivity for AI/ML accelerator SoCs. In addition, a 10X improvement in supply noise immunity greatly eases the SoC power delivery network (PDN) design.

“Our next-generation 112G-LR SerDes on TSMC N5 solution offers 25% power savings, 40% area reduction and better design margins over the previous generation,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “Our close collaborations with leading hyperscale and data center customers have given us the insights into the stringent industry requirements, resulting in a new design with enhanced architecture that offers improvements on all the key parameters for 112G SerDes and network switches. Our 112G-LR SerDes solution on TSMC’s N5 process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the benefits associated with the TSMC N5 process technology.”

The 112G-LR SerDes IP on TSMC’s N5 process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design strategy, which enables advanced-node SoC design excellence.

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