Highlights:
- Cadence optimized its AI-driven RTL-to-GDS digital flow and delivered corresponding 5nm and 3nm RAKs for the Arm Neoverse V2 platform, enabling designers to get to market faster
- Cadence AI-driven verification full flow provides Neoverse V2 platform designers with optimal verification throughput and preparedness for Arm SystemReady compliance
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced an expanded collaboration with Arm to speed data center silicon success on the Arm® Neoverse™ V2 platform. Through the collaboration, Cadence fine-tuned its AI-driven RTL-to-GDS digital flow for Neoverse V2 and delivered corresponding 5nm and 3nm Rapid Adoption Kits (RAKs), empowering customers to achieve power, performance and area (PPA) targets faster. In addition, the Cadence® AI-driven verification full flow supports Neoverse V2, providing designers with optimal verification throughput and preparedness for Arm SystemReady compliance.
Cadence AI-Driven Digital Full Flow for the Neoverse V2 Platform
The comprehensive AI-driven Cadence RTL-to-GDS digital full flow RAKs for 3nm and 5nm nodes includes the Genus™ Synthesis Solution, Modus DFT Software Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Tempus™ Timing Solution and ECO Option, Voltus™ IC Power Integrity Solution, Conformal® Equivalence Checking, Conformal Low Power and the AI-based Cadence Cerebrus™ Intelligent Chip Explorer.
The digital RAKs provide Arm Neoverse V2 designers with several key benefits. For example, the Cadence Cerebrus AI capabilities automate and scale digital chip design, delivering better PPA and improving designer productivity. Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster design closure. The RAKs also include a smart hierarchy flow that delivers optimal turnaround times on large, high-performance CPUs. The Tempus ECO technology offers signoff-accurate final design closure based on path-based analysis. Finally, the RAKs incorporate the GigaOpt activity-aware power optimization engine to significantly reduce dynamic power consumption.
Cadence AI-Driven Verification Full Flow Support for Arm Neoverse V2
The Cadence AI-driven verification full flow optimized to support Arm Neoverse V2 includes the Xcelium™ Logic Simulation Platform, Palladium® Enterprise Emulation Platforms, Protium™ Enterprise Prototyping Systems, Helium™ Virtual and Hybrid Studio, Jasper® Formal Verification Platform, Verisium™ Manager Planning and Coverage Closure tools, Perspec™ System Verifier, and VIP and System VIP tools and content for Arm-based designs.
The Cadence verification full flow provides Neoverse V2 designers with pre-silicon server base system architecture (SBSA) compliance verification and optimized PCI Express® (PCIe®) integration. In addition, the Cadence Helium Virtual and Hybrid Studio includes editable virtual and hybrid platform reference designs for Neoverse V2, incorporating Arm Fast Models to jumpstart early software development and verification. The Helium gearshift technology enables customers to position workloads in a high-performance hybrid environment before shifting to a fully accurate RTL environment, offering detailed verification using either the Palladium or Protium platforms.
“The growing demand for complex workloads such as big data analytics, HPC and ML inference requires specialized compute solutions that achieve greater performance and efficiency,” said Eddie Ramirez,vice president of go-to-market, Infrastructure Line of Business at Arm.“Through this latest collaboration, customers can leverage Cadence’s comprehensive digital and verification flows to validate their solutions and bring the power of their Neoverse V2-based products to market faster. Furthermore, silicon partners will get the benefits of these advanced design flows when running their EDA workloads on Arm-enabled servers and cloud instances.”
“Customers are always looking to accelerate the pace of innovation, and the Arm Neoverse V2 platform provides the foundation needed to address advanced compute requirements for data center silicon success,” said Kam Kittrell, vice president, product management in the Digital & Signoff Group at Cadence. “Through our expanded collaboration with Arm, customers using the AI-driven digital full flow 3nm and 5nm RAKs for Neoverse V2 designs benefit from improved productivity and faster time to tapeout. In addition, by optimizing our AI-driven verification full flow, customers have access to all the tools necessary to verify RTL and perform pre-silicon software validation to ensure full system success.”
The Cadence digital and verification flows support the Cadence Intelligent System Design™ strategy, enabling customers to achieve SoC design excellence. To learn more about how to verify your Arm-based designs using digital and verification solutions from Cadence, visit www.cadence.com/go/armsolneoversev2.
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