DesignCon, the premier event in high-speed communications and system design, today announced a new raft of speakers confirmed for the 2021 edition of DesignCon, set for August 16-18 at the San Jose McEnery Convention Center. This year’s conference offers the DesignCon community access to expert-led sessions, panels, tutorials, and accredited education – both free and paid – exploring emerging trends across the global $1 trillion unit semiconductor market.
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Among the newly announced speakers include engineers, technical directors, CTOs, and R&D directors from Ayar Labs, Broadcom, Intel, KAIST, Microsoft Azure, NXP, and Xilinx. “Semiconductor units have bucked the pandemic downturn and are expected to see a new record high in 2021 with a 13% lift in shipments. This growth creates its own unique challenges and opportunities for chip, board, and systems engineers as electronics require increasingly complex components; we are proud to share that this year’s conference is strategically designed to facilitate peer-to-peer connection and address these timely issues,” said Suzanne Deffree, group event director, DesignCon.
The full DesignCon conference comprises 14 tracks, plus additional tracks dedicated to the Drive World and Embedded Systems Conference geared toward automotive electronics and intelligence, embedded hardware, software, and IoT. Beyond providing highly topical and technical education, DesignCon will serve as the engineering family’s reunion for the first time since the pandemic brought in-person connection to an abrupt halt a year and a half ago. Deffree remarked: “We are so excited to bring the community together and celebrate what we’ve achieved and what’s to come—in just a few weeks, we’ll kick the event off with our inaugural Welcome Reception, this year themed like a summer family reunion and offering attendees the chance to reconnect with peers in a manner that hasn’t been available in Silicon Valley since winter 2020.”
A selection of new sessions includes:
Monday, August 16
Tutorial — PCB Design Principles for Implementing High-Density Semiconductor Package Technology, WLP, PLP, 2D, 2.5D & 3D
Manufacturers are looking for higher functionality for their semiconductor packages to better meet their performance and miniaturization goals. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating several already proven functional elements within a single-package outline. This capability has been stimulated by the rapid deployment of new semiconductor packaging innovations from a broad number of domestic and offshore competing companies that understand that new product time-to-market can be the difference between leading and following.
This course addresses the design and assembly challenges for developing and implementing a broad range of high-density semiconductor package methodologies and multiple function System-in-Package (SiP) technologies. Although integrating several semiconductor functions onto a single die element (System-on-Chip) appears to provide a viable solution for some, development cost and time have often proved to be excessive. On the other hand, many companies have realized that wafer and panel-level packaging and integrating mature multiple-die elements within a 2D or 3D configured package prove superior to the multiple function SoC concepts because it maximizes source flexibility, minimizes risk, and significantly reduces development time and cost. Visit here for speaker details.
Tuesday, August 17
Neural Language Model Enables Extremely Fast & Robust Routing on Interposer
This paper proposes a novel channel routing scheme, which automatically designs effective routing solvers without heuristic knowledge. Our method is based on two-stage components, the deep reinforcement learning (DRL) framework for the automation of solver design and Bayesian optimization for fine-tuning the channels routed by the designed solver. The agent of the DRL framework is parametrized by the Transformer, a cutting-edge language model applied to BERT and GPT-3. We represent the channel routing problem as a sequential decision processing, and we take advantage of the powerful sequential processing capabilities of the language model (Transformer).
The trained Transformer becomes a channel routing solver, termed the initial router, which finishes pin-to-pin routing roughly considering signal integrity (SI). Then, the proposed Bayesian optimization scheme, termed the post router fine-tunes the physical parameters of the channel routed by the initial router, considering SI.
Extensive experiments demonstrate that the proposed routing solvers outperform baseline routing algorithms in several test cases, including routing on high bandwidth memory (HBM) interposer at a significantly faster speed. Visit here for speaker details.
Holistic Power Supply Induced Jitter Accumulation Response Surface Modeling for Chiplet Interconnect System
Trying to meet the ever-increasing computing workload demands, monolithic silicon system-on-chip (SOC) has integrated more and more features with the most advanced silicon technology nodes. However, the explosion in computation workload diversity makes no single system fits for all. Chiplet implementation uses a selection of modular dies, referred to as chiplets, to deliver an optimum feature solution. But optimizing the chiplet interconnect is a major challenge.
A new holistic methodology focusing on chiplets interconnect jitter modeling, which uses an analytical expression of power-induced jitter and accumulation, is proposed and developed. The behavior model is correlated to an actual empirical measurement under different conditions of a High Bandwidth Memory (HBM) system platform. The model is then applied to form a set of output jitter Response Surface Model (RSM), which provides a contour to identify critical input parameters. The impact of input factors dependency, such as power noise tone frequencies, amplitudes, channel ground configurations, is examined. Empirical chiplet system measurement data will be used for correlations. Visit here for speaker details.
Wednesday, August 18
Panel — Getting Onboard (& Package) with Photonics: What’ll It Take?
Photonics is becoming relevant, then prevalent, and finally dominant at shorter and shorter distances. Today, telecommunications delivered over kilometers to your home and business travel via fiber optics, an application dominated by photonics. Now photonics has moved into the data center. Massive hyper-scale data centers across the globe struggle with power consumption and cost, heat, bandwidth, and data latency. Replacing copper wire with fiber optics addresses all these issues. The takeover of fiber optics between racks in the data center is largely complete, and fiber has moved onto interconnecting servers in the same rack. So, photonics has already moved from dominance at kilometer distances to prevalence at ten meters distances to relevance at single-meter distances. In 2021, Photonic Integrated Circuits (PIC) will become more commonly commercially available, promising to make photonics relevant at millimeter distances. Work is underway to integrate the photonics, including the laser, on-chip with electronics, moving photonics relevance down to microns. Why hasn’t this happened sooner? Is it inevitable? What are the barriers to bringing photonics onto the board and package? What are the benefits? When will it happen? This panel will discuss all these issues and more. Visit here for speaker details.
PC Board Design for Low EMI for Wireless & IoT
Many products fail EMC compliance testing due to poor PC board layout, routing and stack-up. This session will describe how to design your board for best EMC performance for wireless, cellular and IoT products. We will also feature the teachings of physicist, Ralph Morrison, in the form of a short tribute. Visit here for speaker details.
For the full conference agenda and to plan your event schedule,
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