Brings expertise in performance and reliability monitoring of die-to-die interfaces to the growing UCIe open chiplet ecosystem
proteanTecs, a global leader of deep data analytics for advanced electronics, has joined the UCIe™ (Universal Chiplet Interconnect Express™) Consortium to introduce interconnect health monitoring to the expanding advanced packaging ecosystem.
Launched in March 2022, UCIe™ aims to create a universal interconnect at the package level, addressing a surging “More Than Moore” market which is expected to grow at a CAGR of 19% until 2027.1 The consortium unites industry leaders in building an interoperable, multi-vendor ecosystem and standardizing future generations of die-to-die (D2D) interconnects and protocol connections. UCIe is led by key industry leaders Advanced Semiconductor Engineering, Inc. (ASE), Alibaba Group, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company.
“As we build a vibrant chiplet ecosystem, ensuring compliance and interoperability across chiplets will be an important area of focus for the UCIe Consortium,” says Dr. Debendra Das Sharma, Board Chair at UCIe Consortium. “We welcome the quality and reliability perspective that proteanTecs brings as a Contributor member and are looking forward to their valuable contribution to UCIe going forward.”
“The UCIe Consortium is successfully uniting the industry as we usher in the new era of semiconductor innovation and scaling through advanced packaging,” says Evelyn Landman, co-founder and CTO at proteanTecs. “Participating in the UCIe will enable us to better tailor our interconnect monitoring roadmap to these emerging industry needs, while also sharing our rich experience in providing visibility to the thousands of potential failure points in a heterogenous system, in production and in the field.”
proteanTecs offers a high-resolution interconnect monitoring solution that supports visibility at every stage—from characterization and qualification, assembly and test, to field deployment and operation. Unlike traditional approaches—which rely on low-granularity, pass-fail testing—this market-leading, patented solution delivers parametric lane grading with 100-percent lane and pin coverage.
For more information on proteanTecs’ interconnect monitoring solutions, download these resources:
- On-demand Webinar: “2.5D Packages: How to Monitor Today So They Don’t Fail Tomorrow”
- On-demand Webinar: “Deep Data Quality and Reliability Monitoring of Heterogeneous Packaging”
- White Paper: “Reliability Monitoring of GUC 7nm High Bandwidth Memory (HMB) Subsystem”
1 Yole Développement, High-End Performance Packaging 2022 – Focus 2.5D/ 3D Integration, March 2022.
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