MIPS Announces Availability of its first RISC-V IP core

Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications

As the shift toward RISC-V accelerates across industries, the open standard instruction set architecture (ISA) is ushering a new wave of innovation and collaboration. In an effort to help fuel this trend, MIPS, a leading developer of highly scalable RISC processor IP, has announced availability of the eVocore (™) P8700, the industry’s highest performance, most scalable RISC-V multiprocessor IP. The P8700 has already been licensed for applications including automotive driver assistance systems (ADAS) and autonomous driving.

The eVocore P8700 multiprocessor IP core, which includes best-in-class performance efficiency for use in Software-on-a-Chip (SoC) applications, is one of the first MIPS products based on the RISC-V open ISA.  P8700 is the first RISC-V IP core that provides out-of-order (OOO) processing and coherent multi-threaded, multi-core, multi-cluster scalability – enabling semiconductor companies and OEMs to achieve a new level of RISC-V performance and to further accelerate innovation.

The P8700 combines a deep pipeline with multi-issue OOO execution and multi-threading to deliver outstanding computational throughput. The high level of scalability of the core makes it well suited for compute-intensive tasks across a broad range of markets and applications such as automotive (ADAS, AV, IVI), data center and storage, and high-performance computing (HPC).

“The eVocore family of IP cores including the P8700 represents the continuing evolution of MIPS as we fully embrace RISC-V,” said Desi Banatao, MIPS CEO. “We designed the P8700 to enable customers to take advantage of the power of RISC-V in CPU IP cores that deliver the highest levels of scalability and performance. We believe that our RISC-V P8700 multiprocessor core will help make it possible for companies of all sizes to get to market quickly with innovative SoC solutions.”

Customers can get started designing with P8700 now, with the support of a broad and growing ecosystem of tools and software.

Features of eVocore P8700 include:

  • Scales to 64 clusters, 512 cores and 1,024 harts/threads
  • Single-threaded performance greater than what is currently available in other RISC-V CPU IP
  • Ideal for compute-intensive tasks across a broad range of applications. Including automotive, data center and storage, HPC and more

P8700 also includes powerful safety features for automotive, such as:

  • Perfect balance between safety and performance for performance-efficient ASIL-D systems
  • Robust safety model that can be used for multiple applications (vision, radar, LiDAR, etc.)
  • Internal fault detection and reporting; special fault bus monitor that enables faster system recovery

MIPS’ eVocore P8700 multiprocessors have already been licensed by Mobileye, a leader in the development and deployment of ADAS and autonomous driving technologies and solutions. Mobileye has included the P8700 in its latest generation EyeQ®Ultra Systems on Chips (SoCs). 

“Mobileye’s highly efficient, scalable and proven EyeQ® SoCs are driving a revolution in driver assistance and autonomous vehicle technologies. The new MIPS eVocore CPUs provide not only the unrivaled combination of performance and efficiency that MIPS is known for, but also the differentiation of an open software development environment,” said Elchanan Rushinek, Executive Vice President of Engineering, Mobileye, whose technology is used by multiple car makers.

P8700 is available in both a standard version and automotive version with functional safety features. The automotive version has proven robust safety capabilities for ISO 26262 ASIL-B(D) and ASIL-D systems, taking advantage of Safety Element out-of-Context (SEooC) that reduces time to market.

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